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| QL7180 EclipsePlus Data Sheet ****** Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic * 0.25 m five layer metal CMOS Process * 2.5 V VCC, 2.5/3.3 V Drive Capable I/O * 4,032 Logic Cells * 583,008 Max System Gates * Up to 347 I/O Pins Advanced Clock Network * Nine Global Clock Networks: * One Dedicated * Eight Programmable * 20 Quad-Net Networks--five per Quadrant * 16 I/O Control--two per I/O Bank * Four phase locked loops Embedded Computational Units Embedded Dual Port SRAM * Thirty-six 2,304-bit Dual Port High ECUs provide integrated Multiply, Add, and Accumulate Functions. Performance SRAM Blocks * 82,900 RAM Bits * RAM/ROM/FIFO Wizard for Automatic Configuration * Configurable and Cascadable PLL Memory - Dual Port RAM Embedded Computational Units PLL Programmable I/O * High performance Enhanced I/O (EIO)-- High Speed Logic Cells 583K Gates PLL Memory - Dual Port RAM PLL less than 3 ns Tco * Programmable Slew Rate Control * Programmable I/O Standards: * LVTTL, LVCMOS, PCI, GTL+, SSTL2, Figure 1: EclipsePlus Block Diagram and SSTL3 * Eight Independent I/O Banks * Three Register Configurations: Input, Output, and Output Enable (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 1 QL7180 EclipsePlus Data Sheet Rev C Electrical Specifications AC Characteristics* *(at VCC = 2.5 V, TA = 25 C, Typical Corner, Speed Grade = -7 (K = 1.00)) The AC Specifications are provided from Table 1 to Table 9. Logic Cell diagrams and waveforms are provided from Figure 2 to Figure 15. Figure 2: EclipsePlus Logic Cell Table 1: Logic Cells Symbol Logic Cells tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip flop must be stable before the active clock edge Hold time: time the synchronous input of the flip flop must be stable after the active clock edge Clock to out delay: the amount of time taken by the flip flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal remains high/low Reset Width: time that the RESET signal remains high/low Parameter Value (ns) Min 0.205 0.231 0 0.46 0.46 0.3 0.3 Max 1.01 0.427 0.585 0.658 - 2 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C SET D CLK RESET Q Figure 3: Logic Cell Flip-Flop CLK tCWHI (min) SET tCWLO (min) RESET Q tRESET tRW tSET tSW Figure 4: Logic Cell Flip-Flop Timings--First Waveform CLK D tSU tHL Q tCO Figure 5: Logic Cell Flip-Flop Timings--Second Waveform (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 3 QL7180 EclipsePlus Data Sheet Rev C Quad net Figure 6: EclipsePlus Global Clock Structure Table 2: Eclipse Global Clock Tree Delays Clock Segment Parameter Max. Rise tPGCK tBGCK Global clock pin delay to quad net Global clock buffer delay (quad net to flip flop) 0.990 0.534 Value (ns) Max. Fall 1.386 1.865 Programmable Clock External Clock Global Clock Buffer Global Clock Clock Select tPGCK tBGCK Figure 7: Global Clock Structure Schematic 4 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C [9:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD RAM Module [9:0] [17:0] Figure 8: RAM Module Table 3: RAM Cell Synchronous Write Timing Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD Parameter Value (ns) Min 0.675 ns 0 ns 0.654 ns 0 ns 0.276 ns 0 ns Max 2.796 ns WCLK WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA Figure 9: RAM Cell Synchronous Write Timing (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 5 QL7180 EclipsePlus Data Sheet Rev C Table 4: RAM Cell Synchronous & Asynchronous Read Timing Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD Parameter Value (ns) Min 0.686 ns 0 ns 0.243 ns 0 ns Max 2.225 ns RAM Cell Asynchronous Read Timing rPDRD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 2.405 ns RCLK RA tSRA RE tSRE RD old data tHRE new data tHRA tRCRD rPDRD Figure 10: RAM Cell Synchronous & Asynchronous Read Timing 6 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C + INPUT REGISTER QE R D OUTPUT REGISTER D R Q PAD OUTPUT ENABLE REGISTER D EQ R Figure 11: EclipsePlus Cell I/O tISU + tSID QE R D PAD Figure 12: EclipsePlus Input Register Cell (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 7 QL7180 EclipsePlus Data Sheet Rev C Table 5: Input Register Cell Symbol Input Register Cell Only tISU tIHL tICO tIRST tIESU tIEH Input register setup time: time the synchronous input of the pin must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge Parameter Value (ns) Min 3.308 ns 0 ns 0.830 ns 0 ns Max 3.526 ns 0.494 ns 0.464 ns 0.987 ns - Table 6: Standard Input Delays Symbol Standard Input Delays tSID (LVTTL) tSID (LVCMOS2) tSID (GTL+) tSID (SSTL3) tSID (SSTL2) Parameter To get the total input delay add this delay to tISU LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V Value Min Max 0.34 ns 0.42 ns 0.68 ns 0.55 ns 0.61 ns R CLK D tISU t t IHL ICO t IRST Q E t IESU t IEH Figure 13: EclipsePlus Input Register Cell Timing 8 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C PAD OUTPUT REGISTER Figure 14: EclipsePlus Output Register Cell Table 7: EclipsePlus Output Register Cell Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-State Output Delay low to tri-State Clock-to-out delay (does not include clock tree delays) Parameter Min Value Max 0.40 ns 0.55 ns 2.94 ns 2.34 ns 3.07 ns 2.53 ns 3.15 ns (fast slew) 10.2 ns (slow slew) (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 9 QL7180 EclipsePlus Data Sheet Rev C H L H Z L H Z L tOUTLH H L H tPZH Z L H Z L tOUTHL tPZL tPHZ tPLZ Figure 15: EclipsePlus Output Register Cell Timing Table 8: Output Slew Rates @ VCCIO = 3.3 V Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns Table 9: Output Slew Rates @ VCCIO = 2.5 V Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns NOTE: For tips to minimize ground bounce, refer to Application Note 66 at ht t p : // ww w. q ui ckl o gi c . c om /imag es/appnote 66.pdf . 10 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C DC Characteristics The DC Specifications are provided in Table 10 through Table 13. Table 10: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage INREF Voltage Input Voltagea Latch-up Immunity Value -0.5 V to 3.6 V -0.5 V to 4.6 V 2.7 V -0.5 V to VCCIO +0.5 V 100 mA Parameter DC Input Current ESD Pad Protection Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature Value 20 mA 2000 V -65 C to + 150 C -55 C to + 125 C a. All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). Table 11: Operating Range Symbol Parameter Military Min VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -4 Speed Grade K Delay Factor -5 Speed Grade -6 Speed Grade -7 Speed Grade 2.3 2.3 -55 0.42 0.42 0.42 0.42 125 2.3 1.92 1.35 1.27 Max 2.7 3.6 Industrial Min 2.3 2.3 -40 0.43 0.43 0.43 0.43 Max 2.7 3.6 85 2.16 1.80 1.26 1.19 Commercial Min 2.3 2.3 0 0.47 0.46 0.46 0.46 Max 2.7 3.6 70 2.11 1.76 1.23 1.16 V V C C n/a n/a n/a n/a Unit (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 11 QL7180 EclipsePlus Data Sheet Rev C Table 12: DC Characteristics Symbol II IOZ CI IOS ICC ICCIO ICCIO(DIF) IREF IPD Parameter I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance a Conditions VI = VCCIO or GND VI = VCCIO or GND Vo = GND Vo = VCC VI,Vo = VCCIO or GND VCCIO = 3.6 V Min -10 -10 -15 40 0.50 (typ) 0 -10 - Max 10 10 8 -180 210 2 2 10 150 Units A A pF mA mA mA mA mA A A Output Short Circuit Currentb D.C. Supply Currentc D.C. Supply Current on VCCIO D.C. Supply Current on VCCIO for Differential I/O D.C. Supply Current on INREF Pad Pull-down (programmable) a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -4/-5/-6/-7 commercial grade devices only. See Table 13 for more details on ICC characteristics. Table 13: ICC Characteristics Temperature Characteristic Condition Commercial ICC VCCPLL = GND VCCPLL = VCC 2 mA (max) 3.25 mA (max) Industrial 3 mA (max) 5 mA (max) Military 5 mA (max) 10 mA (max) NOTE: If PLLs are not used, the VCCPLL and PLLRST pins may be grounded to the lower ICC for the device. 12 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Embedded Computational Unit (ECU) Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively--these functions require high logic cell usage while garnering only moderate performance results. The QL7180 architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL7180 device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 16. RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[0:16] 3-4 decoder C B A A[0:7] A[8:15] 8-bit Multiplier 2-1 mux 16-bit Adder D Q 17 inc. 17-bit COUT Register A[0:15] CLK B[0:15] 2-1 mux Figure 16: ECU Block Diagram The 18 QL7180 ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Eighteen 8-bit MAC functions can be implemented per cycle for a total of 1.8 billion MACs when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The modes for the ECU block are dynamically re-programmable through the programmable logic. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 13 QL7180 EclipsePlus Data Sheet Rev C Table 14: ECU Mode Select Criteria Instruction Operation S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Multiply Multiply-Add Accumulatec Add Multiply (registered)d Multiply- Add (registered) Multiply - Accumulate Add (registered) 3.14 ns max 9.61 ns min 9.61 ns min 9.61 ns min 3.91 ns min 1.16 ns max 1.16 ns max 1.16 ns max 1.16 ns max ECU Performancea, t -7 WCCb t PD t SU CO 6.57 ns max 8.84 ns max 3.91 ns min 1.16 ns max a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Timing numbers represent -7 Worst Case Commercial conditions. c. Internal feedback path in ECU restricts max clk frequency to 238 MHz. d. B [15:0] set to zero. 14 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Phase Locked Loops (PLLs) Instead of requiring extra components, designers simply need to instantiate one of the preconfigured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. Also, QuickLogic PLLs can be cascaded to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. Most importantly, they achieve a very short clock-to-out time--generally less than 3 ns. This low clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero. Figure 17 illustrates a typical QuickLogic ESP PLL. 1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree Frequency Multiply . _1 . . _2 . . _4 . FOUT Figure 17: PLL Block Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 17) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 17). The charge pump generates an error voltage to bring the VCO back into alignment and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 15 QL7180 EclipsePlus Data Sheet Rev C Fout represents the clock signal that emerges from the output pad (the output signal PLLPAD_OUT is explained in Table 16). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it remains in high Z state, as shown in the postsimulation waveform. Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL presented in Figure 17 controls the clock tree in the fourth Quadrant of its ESP. As previously mentioned, QuickLogic PLLs compensate for the additional delay created by the clock tree itself by subtracting the clock tree delay through the feedback path. For more specific information on the Phase Locked Loops, please refer to Application Note 58 at ht t p : // ww w.q ui ckl o gi c . c o m /i m ag e s /ap p no te 5 8 . pd f PLL Modes of Operation QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency--Table 15 indicates the features of each mode. Table 15: PLL Mode Frequencies PLL Model PLL_HF b Output Frequency Same as input frequency Same as input frequency 2 Input Frequency Rangea 66 MHz-150 MHz 25 MHz-133 MHz 50 MHz-125 MHz 16 MHz-50 MHz 100 MHz-250 MHz 50 MHz-100 MHz 16 MHz-40 MHz 100 MHz-300 MHz Output Frequency Range 66 MHz-150 MHz 25 MHz-133 MHz 100 MHz-250 MHz 32 MHz-100 MHz 50 MHz-125 MHz 25 MHz-50 MHz 64 MHz-160 MHz 25 MHz-75 MHz PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 x input frequency 2 x input frequency 1/2 x input frequency 1/2 x input frequency 4 x input frequency 1/4 x input frequency a. The input frequency can range from 12.5 MHz to 500 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies. b. HF stands for high frequency and LF stands for low frequency. 16 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C PLL Signals Table 16 summarizes the key signals in QuickLogic's PLLs. Table 16: PLL Signals Signal Name PLLCLK_INa PLLRST Input clock signal Active High Reset If PLLRST is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip. This is a static signal, not a dynamic signal. ONn_OFFCHIP Tied to GND = outgoing signal drives internal gates. Tied to VCC = outgoing signal used off-chip. CLKNET_OUT Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND. Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be tied to VCC. Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the RESET signal. Description PLLCLK_OUT PLLPAD_OUT LOCK_DETECT a. Because PLLCLK_IN and PLLRST signals have INPAD, and PLLPAD_OUT has OUT- PAD, you do not have to add additional pads to your design. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 17 QL7180 EclipsePlus Data Sheet Rev C I/O Characteristics IOL vs VOL 180 Vccio = 3.6V 160 140 120 Vccio = 3.3V Vccio = 3.0V Vccio = 2.7V Vccio = 2.5V Vccio = 2.3V Current (mA) 100 80 60 40 20 0 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 Supply voltage (V) Figure 18: IOL vs. VOL IOH vs VOH 20 0 3. 30 3. 50 2. 70 2. 90 3. 00 1. 90 2. 10 2. 30 0. 50 0. 90 1. 30 1. 50 0. 00 0. 10 0. 30 1. 70 0. 70 1. 10 2. 50 3. 10 3. 60 -20 Current (mA) -40 VccI/O = 2.3V VccI/O = 2.5V -60 VccI/O = 2.7V VccI/0 = 3.0V VccI/O = 3.3V -80 -100 VccI/O = 3.6V -120 Supply voltage (V) Figure 19: IOH vs. VOH 18 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Table 17: DC Input and Output Levelsa INREF VMIN LVTTL LVCMOS2 GTL+ PCI SSTL2 SSTL3 n/a n/a 0.88 n/a 1.15 1.3 VMAX n/a n/a 1.12 n/a 1.35 1.7 VMIN -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 INREF - 0.2 0.3 x VCCIO INREF - 0.18 INREF - 0.2 VMIN 2.0 1.7 INREF + 0.2 0.5 x VCCIO INREF + 0.18 INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.5 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.6 0.1 x VCCIO 0.74 1.10 VOH VMIN 2.4 1.7 n/a 0.9 x VCCIO 1.76 1.90 IOL mA 2.0 2.0 40 1.5 7.6 8 IOH mA -2.0 -2.0 n/a -0.5 -7.6 -8 a. The data provided in Table 17 are JEDEC and PCI Specifications. QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see Table 1 through Table 13 and Figure 1 through Figure 17 NOTE: All CLK and IOCTRL pins are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. NOTE: All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). Table 18: Max I/O per Device /Package Combination Device QL7180 280 BGA 163 484 BGA 327 516 BGA 347 (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 19 QL7180 EclipsePlus Data Sheet Rev C Package Thermal Characteristics Thermal Resistance Equations: JC = (TJ - TC)/P JA = (TJ - TA)/P PMAX = (TJMAX - TAMAX)/ JA Parameter Description: JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature NOTE: Maximum junction temperature (TJMAX) is 150 C. To calculate the maximum power dissipation for a device package look up JA from Table 19, pick an appropriate TAMAX and use: PMAX = (150 C - TAMAX)/ JA Table 19: Package Thermal Characteristics Package Description Pin Count Package Type 516 484 280 PBGA PBGA LF-PBGA JA (C/W) @ various flow rates (m/sec) JC (C/W) 0 20.0 28.0 18.5 0.5 19.0 26.0 17.0 1 17.5 25.0 15.5 2 16.0 23.0 14.0 7.0 9.0 7.0 20 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Kv and Kt Graphs Voltage Factor vs. Supply Voltage 1.1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 Supply Voltage (V) Figure 20: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 Kt 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Junction Temperature C Figure 21: Temperature Factor vs. Operating Temperature (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 21 QL7180 EclipsePlus Data Sheet Rev C Power vs. Operating Frequency The basic power equation which best models power consumption is given below: PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] (mW) CKLD + Where * * * * * * * LC is the total number of logic cells in the design CKBF = # of clock buffers CLBF = # of column clock buffers CKLD = # of loads connected to the column clock buffers RAM = # of RAM blocks PLL = # of PLLs INP is the number of input pins * OUTP is the number of output pins Figure 22 exhibits the power consumption in an EclipsePlus QL7180 device. The chip was filled with (300) 8-bit countersapproximately 76% logic cell utilization. 2.5 Power vs Freq. (Counter_300) 2 Power (W) 1.5 1 0.5 0 0 20 40 60 80 100 120 140 Frequency (Mhz) Figure 22: Power Consumption Figure 23 illustrates the theoretical worst-case scenarios for 50%, 70%, and 90% utilizations of the 6500-516 package. The resources of the device are divided exactly in half; meaning, for 50% utilization, exactly 50% of the I/Os, Logic Cells, RAM blocks, clock network, etc. are utilized. These situations may never occur in a real design, but they do provide a very rough quantitative measure of power consumption when talking in terms of 50% or 70% utilization of an EclipsePlus device. 22 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Power vs. Frequency 7 6 5 Power (W) 4 3 2 1 0 0 50 100 150 Frequency (Mhz) 50% 70% 90% 200 250 300 Figure 23: Power vs. Frequency (Absolute 50%, 70%, and 90% of the Available Resources on Chip) To learn more about power consumption, please refer to application note #60 which is located at http://www.quicklogic.com/images/appnote60.pdf. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 23 QL7180 EclipsePlus Data Sheet Rev C Power-up Sequencing VCCIO Voltage VCC (VCCIO -VCC)MAX VCC 400 us Figure 24: Power-up Requirements When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value (refer to Figure 24). NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (VCCIO -VCC)MAX 500 mV when ramping up the power supply. 24 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Joint Test Access Group (JTAG) TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Figure 25: JTAG Block Diagram Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 25 QL7180 EclipsePlus Data Sheet Rev C The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. 26 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Pin Descriptions Table 20: JTAG Pin Descriptions Pin TDI/RSI TRSTB/RRO TMS TCK TDO/RCO Function Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG/RAM init. clock out Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VCC if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization NOTE: All JTAG inputs are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). All JTAG outputs are driven by the VCC rail, not VCCIO. Therefore, these output pins can only drive up to VCC + 0.3 V. These output pins are LVCMOS2 compliant only (2.5 V). IOCTRL(A) IOCTRL(A) VCCIO (A) INREF(A) VCCIO (A) INREF(A) IO(A) IO BANK A VCCIO (H) INREF(H) IOCTRL(H) IO(H) IO BANK B VCCIO (C) INREF(C) IOCTRL(C) IO(C) IO BANK H IO(A) IO BANK C IO BANK G VCCIO (G) INREF(G) IOCTRL(G) IO(G) VCCIO (D) INREF(D) IOCTRL(D) IO(D) IO BANK D IO BANK F IO BANK E INREF(E) IO(E) INREF(F) IO(F) VCCIO (E) IOCTRL(E) Figure 26: I/O Banks with Relevant Pins VCCIO (F) IOCTRL(F) (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 27 QL7180 EclipsePlus Data Sheet Rev C Table 21: Dedicated Pin Descriptions Pin Direction Function Description Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The I/O pin is a bi-directional pin, configurable to either an inputonly, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Connect to 2.5 V supply This pin provides the flexibility to interface the device with either a 3.3 V device or a 2.5 V device. The A inside the parenthesis means that VCCIO is located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will output VCCIO level signals. This pin must be connected to either 3.3 V or VCC. CLKa I Global clock network driver I/O(A) I/O Input/Output pin VCC I Power supply pin VCCIO(A) I Input voltage tolerance pin VCCPLL b I Connect to 2.5 V supply. VCCPLL should be connected to 2.5 V Phase locked loop power supply supply if the PLLs are used. If the PLLs are not used, VCCPLL can be connected to 2.5 V supply or GND. See Table 13 for for ICC pin differences when VCCPLL is connected to 2.5 V or GND. Ground pin PLL clock input Dedicated clock pin Ground pin for PLL Connect to ground Clock input for PLL Low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g. RAM, Flip Flops). Connect to GND The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 17 for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if not needed. Dedicated PLL output pin. Otherwise may be left unconnected Reset input for PLL. If PLLs are not used, PLLRST should be connected to the same voltage as VCCPLL (e.g., VCC or GND). This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. This pin should be tied to GND or VCC if it is not used. GND PLLINa DEDCLKa GNDPLL I I I I INREF(A) I Differential reference voltage PLLOUT PLLRSTa O I PLL output pin Reset input pin for PLL IOCTRL(A)a I Highdrive input a. All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). b. All PLLOUT output pins are driven by the VCC rail, not the VCCIO rail. These output pins are LVCMOS2 compliant only (2.5 V). 28 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C Recommended Unused Pin Terminations for the EclipsePlus devices All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 22. Table 22: Recommended Unused Pin Terminations Signal Name PLLOUT INREF a. x represents a number. b. y represents an alphabetical character. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 29 QL7180 EclipsePlus Data Sheet Rev C 280 PBGA Pinout Diagram Top EclipsePlus QL7180-4PT280C Bottom Pin A1 Corner 30 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C 280 PBGA Pinout Table Table 23: 280 PBGA Pinout Table PBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT<3> GNDPLL<0> I/O PBGA C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK<5>/PLLI N<3> VCCIO PBGA E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL PBGA K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O PBGA R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O PBGA U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O IOCTRL VCCIO I/O TDO PLLRST<2> I/O PLLOUT<2> GNDPLL<3> GND I/O I/O IOCTRL I/O I/O I/O CLK<1> CLK<4>DEDC LK/PLLIN<0> I/O I/O INREF I/O I/O I/O GNDPLL<2> GND GND PLLRST<3> I/O I/O I/O I/O I/O I/O TDI CLK<2>/PLLI N<2> I/O I/O I/O IOCTRL I/O I/O I/O I/O PLLOUT<1> (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 31 QL7180 EclipsePlus Data Sheet Rev C 280 PBGA Packaging Drawing Figure 27: 280 PBGA Packaging Drawing 32 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL7180 EclipsePlus Data Sheet Rev C 484 PBGA Pinout Diagram Top EclipsePlus QL7180-4PS484C Bottom 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Pin A1 Corner (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 33 QL7180 EclipsePlus Data Sheet Rev C 484 PBGA Pinout Table Table 24: 484 PBGA Pinout Table PBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Function I/O PLLRST<3> I/O I/O I/O I/O PBGA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Function I/O I/O VCCPLL<3> PLLOUT<2> I/O I/O |